A proposed structure of an integrated circuit device includes a stacked structure formed by stacking f a plurality of flash memory chips having flush memory (see, for example, Non-Patent Document 1). This proposed integrated circuit device successively performs down-sizing the device by stacking a plurality of flash memory chips.
Non-Patent Document 1: Tanaka et al. “NAND-type flash Memory”, TOSHIBA REVIEW, 2008. vol. 63 No 2. pp. 28-31.